The present invention relates to a semiconductor device that functions as a DTMOS or MISFET having a heterojunction type active region and, more particularly, a semiconductor device that operates at a low supply voltage.
Battery-driven portable personal digital assistances have come into wide use in recent years. For such devices, there is a strong demand for a reduction of supply voltages without sacrificing high-speed operations to prolong the battery life. In order to realize a high-speed operation even at a low supply voltage, it is effective to reduce a threshold voltage. In this case, there is naturally a lower limit to the threshold voltage because a leakage current when the gate is OFF increases.
Thus, as disclosed, for example, in a document xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d (F. Assaderaghi et al., IEDM94 Ext. Abst. p.809), a device called DTMOS (Dynamic Threshold Voltage MOSFET) is proposed which solves the above described problem, provides a small leakage current even at a low voltage and has high drive performance.
A conventional DTMOS includes a gate insulating film provided on an active region of a semiconductor substrate, a gate electrode, source and drain regions provided in region located at both sides of the gate in the active region and a channel region provided in a region between the source and drain regions of the substrate active region. A substrate region (body region) located below or beside the channel region is connected to the gate electrode using a wire so that the two are electrically short-circuited. Then, when a bias voltage is applied to the gate with the gate and body short-circuited, a forward bias voltage as high as the gate bias voltage is applied to the channel region through the body. This creates a state similar to that of a normal MOS transistor when the gate bias is OFF. On the other hand, when the gate bias is ON, the body is biased in the forward direction as the gate bias voltage increases, and therefore the threshold voltage decreases.
When compared to an ordinary MOS transistor (transistor whose gate is not short-circuited with the body) formed on an SOI substrate, such a DTMOS has a leakage current equivalent to the leakage current of the ordinary transistor when the gate bias is OFF. On the other hand, when the gate bias is ON, as described above, the threshold decreases, and therefore a gate-over-drive effect increases and the drive force increases significantly. Furthermore, since there is little potential difference between the gate and channel region of the DTMOS, the electric field in the longitudinal direction on the surface of the substrate becomes extremely small compared to the ordinary transistor. As a result, the deterioration of mobility of carriers with the increase of the electric field in the longitudinal direction is suppressed, which increases the drive force significantly.
Thus, the DTMOS functions as a transistor capable of a high-speed operation at a low threshold voltage, that is, a low supply voltage within an operating voltage range after a transverse parasitic bipolar transistor generated between the source region (emitter), body (base) and drain region (collector) turns ON and grows to such an extent that the substrate current becomes problematic from a practical standpoint.
However, according to the above described conventional DTMOS, the source and channel/body are biased in the forward direction with the increase of the gate bias voltage, and therefore a current called xe2x80x9csubstrate currentxe2x80x9d flows between the source and channel/body and gate. Thus, it is preferable for the DTMOS to suppress this substrate current and at the same time reduce the threshold to thereby secure a wide operating voltage range. Since it is possible to assume a simple model in which PN junction diodes exist between the source and body and between the source and channel, the substrate current is determined by the material of the semiconductor (band gap) and concentration of impurities in the junction region. Since the source region is generally doped with impurities of high concentration on the order of 1xc3x971020 atomsxc2x7cmxe2x88x923, if the concentration of impurities of the body is increased, it is possible to suppress the source-body component of the substrate current.
However, since the threshold also increases as the concentration of impurities of the body increases, it is actually difficult to secure a wide operating voltage range by increasing the concentration of impurities of the body.
It is an object of the present invention to provide a semiconductor device capable of increasing concentration of impurities of the body region and with a small substrate current and a wide operating voltage range.
A first semiconductor device of the present invention is provided with a semiconductor layer including at least a first semiconductor film, a second semiconductor film having a band gap different from that of the first semiconductor film constructed in such a way that the band gap decreases from the location next to the first semiconductor film in the direction away from the first semiconductor film, a gate insulating film provided on the semiconductor layer, a gate electrode provided on the gate insulating film, source and drain regions formed by introducing a first conductive type impurity to the region located at both sides of the gate electrode of the semiconductor layers, a channel region formed by introducing a second conductive type impurity to a region located between the source and drain regions of the second semiconductor film, a body region formed by introducing a second conductive type impurity which has higher concentration than the channel region to a region located between the source and drain regions of the second semiconductor film and a conductive member for electrically connecting the gate electrode and body region.
In this way, a potential recess (well) is formed at the band edge where second conductive type carriers run in the part located in the source and drain regions of the second semiconductor film, which secures a low threshold voltage and reduces an overall substrate current.
The first semiconductor film above is preferably made up of a semiconductor whose composition is expressed as Si1xe2x88x92x1xe2x88x92y1Gex1Cy1 (0xe2x89xa6x1 less than 1, 0xe2x89xa6y1 less than 1) and the second semiconductor film above is preferably made up of a semiconductor whose composition is expressed as Si1xe2x88x92x2xe2x88x92y2Gex2Cy2 (0xe2x89xa6x2xe2x89xa61, 0xe2x89xa6y2xe2x89xa61, x2+y2 greater than 0).
The above first semiconductor film is made of silicon and the above second semiconductor film is made of a semiconductor whose composition is expressed as Si1xe2x88x92x3Gex3 (0 less than x3xe2x89xa60.4) and the Ge composition ratio of the above second semiconductor film increases from the location neighboring the first semiconductor film upward, and therefore a large band offset is formed at the edge of a valence band of the channel region and it is possible to obtain a structure appropriate for a p-channel type transistor.
The above described first semiconductor film is made of silicon, the second semiconductor film is made of semiconductor whose composition is expressed as Si1xe2x88x92y3Cy3 (0 less than y3xe2x89xa60.03), and because the C composition ratio of the second semiconductor film increases from the location adjacent to the first semiconductor film upward, a large band offset is formed at the edge of the conduction band of the channel region, which makes it possible to obtain a structure suitable for an n-channel type transistor.
The above described first semiconductor film is made of silicon, the second semiconductor film is composed of Si1xe2x88x92x4xe2x88x92y4Gex4Cy4 (0 less than x4xe2x89xa60.4, 0 less than y4xe2x89xa60.03), and therefore it is possible to obtain a structure suitable for both n-channel type and p-channel type transistors.
The above described first conductive type is an n-type and second conductive type is a p-type, and of the substrate current that flows from the body region into the region located in the source and drain regions of the first semiconductor film, the component to which holes contribute is preferably smaller than the component to which electrons contribute.
The above described first conductive type is a p-type and second conductive type is an n-type, and of the substrate current that flows from the body region into the region located in the source and drain regions of the first semiconductor film, the component to which electrons contribute is preferably smaller than the component to which holes contribute.
The above described semiconductor layer further includes a third semiconductor film provided between the first semiconductor film and second semiconductor film, and further includes a buffer region that includes a second conductive type impurity of lower concentration than the body region or an undoped buffer region provided in the region located between the source and drain regions of the third semiconductor film, and therefore in the part located in the source and drain regions of the second semiconductor film, the potential recess at the edge of the band where the second conductive type carriers run goes away from the body region, which suppresses the substrate current.
It is preferable that the above described semiconductor layer be further provided with an Si cap region between the second semiconductor film and the gate insulating film.
Provision of the additional insulating layer under the first semiconductor film makes it possible to obtain a semiconductor device that operates especially fast.
The second semiconductor device of the present invention is provided with a semiconductor layer including at least a first semiconductor film, a second semiconductor film placed on the first semiconductor film having smaller potential with respect to carriers at the edge of the band through which carriers run than the first semiconductor film and a third semiconductor film between the first semiconductor film and second semiconductor film, agate insulating film provided on the semiconductor layer, a gate electrode provided on the gate insulating film, source and drain regions formed by introducing a first conductive type impurity to regions located at both sides of the gate electrode of the semiconductor layer, a channel region formed by introducing a second conductive type impurity to a region located between the source and drain regions of the second semiconductor film, a body region formed by introducing a second conductive type impurity of higher concentration than that of the channel region to a region located between the source and drain regions of the second semiconductor film, a buffer region including a second conductive type impurity of lower concentration than that of the body region or an undoped buffer region provided in a region located between the source and drain regions of the third semiconductor film and a conductive member for electrically connecting the gate electrode and body region.
This forms a potential recess (well) at the edge of the band through which the second conductive type carriers run in the part of the second semiconductor film located between the source and drain regions, but since the third semiconductor film is provided, the distance between this potential recess and the first semiconductor film increases. On the other hand, due to the built-in potential of the band on the longitudinal plane that passes through the gate electrode of the semiconductor device, the band is bent in the direction that interferes with the movement of the second conductive type carriers in the body region as it goes away from the first semiconductor film. This prevents the second conductive type carriers in the body region from passing through the channel region made up of the second semiconductor film and entering the part of the second semiconductor film which is located between the source and drain regions, thus reducing an overall substrate current.
The thickness of the third semiconductor film is preferably 15 nm or more or more preferably 30 nm or more.